LCEVC Decoder IP Core

V-Nova LCEVC decoder IP core is a versatile solution that supports high resolutions up to 4K, 8K, or even 16K, with frame rates 60 -120 fps. It includes optional frame buffer compression to minimize memory requirements. Through the use of AXI MM and AXI Streaming interfaces, it can easily adapt to different interface protocols. It has been compiled for and verified on Xilinx Alveo U50 and U250 boards, guaranteeing reliability and performance.

The LCEVC Decoder Core features interfaces for efficient data transfer, communication with the host, and streaming of decoded output. By leveraging LCEVC decoder IP core, you can easily incorporate LCEVC into your next generation video SoC and take advantage of its enhanced video coding capabilities.

Design Features of the V-Nova LCEVC Decoder IP

At the heart of the V-Nova LCEVC Decoder IP are distinctive design features to address the video decoding needs of different applications and SOC architectures:

MPEG-5-part2 LCEVC Specification Compliance

Foremost among these features is the Decoder IP's meticulous alignment with the MPEG-5-part2 LCEVC specification (ISO/IEC 23094-2). This adherence ensures complete compatibility with all defined features and profiles.

Adaptable Integration Architecture

Additionally, the Decoder IP has been designed with adaptability in mind. This includes the parametrization of vital metrics such as maximum resolution, performance throughput, latency, logic area, and DDR bandwidth availability. This flexible approach enables integrators to tailor the Decoder IP's configuration to align precisely with their project's unique requirements.

Input and Output Flexibility

The Decoder IP has also been designed to support a multitude of base decoders with diverse characteristics. Additionally, the Decoder IP offers a runtime selection feature that allows users to choose between writing the output to DDR memory or streaming it directly to the display.

High Performance

The Decoder IP design targets high performance metrics to satisfy the most demanding applications. It reaches a maximum throughput of 16K resolution at 120 frames per second, accommodating 4:4:4 14-bit per pixel video formats. The design flexibility extends to the configuration of epth, with choices between 8 or 16, as well as the internal parallelization factor Pixels-Per-Clock (PPC), offering options of 8, 16, or 32. Furthermore, the integration system clock is tailored to meet the demands of different resolutions, with 200MHz for resolutions up to 4Kp60 and 800MHz for resolutions of 8K and beyond.

LCEVC Decoder IP Architecture Options

AXI-MM, AXI-Lite and AXI-S interfaces are provided: AXI-4 for data access and transfers, AXI-Lite for communication with the Host Controller, AXI-Stream optionally for streaming the final enhanced decoded output

The LCEVC Decoder IP offers two setup options:

1. Serial Processing Design (Minimum Resource Usage): This architecture conserves resources, suiting scenarios prioritizing efficiency and resource minimization.

2. Parallel Processing Architecture (Maximum Speed): Designed for optimal decoding speed and latency, this architecture utilizes more resources to enhance processing performance.

Advanced Configurations and Frame Buffer Compression:

To minimize memory utilisation for 16K or 8K resolutions or 120 fps video, it is recommended to integrate V-Nova's frame buffer compression. This will increase logic resource utilization, requiring careful consideration.

V-Nova Integration Services team can also work to further adapt the architecture and include proprietary frame buffer compression solutions.

LCEVC Decoder Integration

A typical integration of the LCEVC decoder core

Integrating the LCEVC Decoder IP involves a series of steps:

1. Extracting LCEVC from the Video Stream: The process involves using a Stream Demux block to separate the input video stream into two separate elementary components: the base codec compressed frames and LCEVC enhancement frames.

2. Storage in Frame Buffers: These frames are then stored in dedicated frame buffers within the SDRAM.

3. Base Decoding: The Base decoder performs the decoding of base frames and stores the reconstructed base frames in designated Recon frame stores, also situated in SDRAM.

4. LCEVC Read: The LCEVC decoder core accesses both the LCEVC enhancement frames and the decoded base frames from the SDRAM frame buffers.

5. Final Output Options: Ultimately, the LCEVC decoder offers two output options for the decoded video frames:

   • SDRAM frame buffer.

   • Streaming output interface (if present).

The diagram below shows the LCEVC Decoder IP inside a typical SOC implementation: